Timing optimization of a logic network is typically performed using an integrated incremental timing analyzer, and is invoked at different stages of the design process, e.g., before placement, and after placement and routing. A benefit of this approach is that the design changes that are required to correct large problems can be made before subsequent expensive design stages such as placement and routing, reducing the computational expense that would otherwise be required to incrementally update the design decisions made during these subsequent processes.
Coupling between nets can affect the timing of a logic network, and its impact on the timing analysis must be assessed to drive timing optimization. During coupling, pairs of nets are considered, in which one net is an “aggressor,” on which a signal transition can, through capacitive or inductive coupling, alter the timing of a transition on another “victim” net. By way of example, U.S. Pat. Nos. 6,615,395 and 6,651,229 provide more details on the effect of coupling to the static timing analysis.
Coupling is the cause of both timing violations (failure of signals to meet timing requirements) and electrical violations (e.g., excessive signal slew and transition time or excessive effective load capacitance on a driver). The majority of those violations can be repaired by simple techniques, such as sizing up the driver gate of the victim net.
True coupling analysis requires information about nets being coupled (i.e., which pairs of nets are in close proximity of each other to interact), hence coupling violations can only be identified accurately after routing and electrical parasitic extraction. Even when routing information is available, it is difficult and expensive to incrementally update the impact of certain effects, like coupling on the timing results. Methods have been proposed to efficiently approximate these coupling effects during incremental static timing, as described, e.g., in U.S. patent application Ser. No. 11/420,529, herein incorporated by reference in its integrity. However, these methods still cannot operate until routing has been performed.
Post-routing timing closure (optimizing or modifying a design to correct all the timing violations) is becoming one of the biggest turn-around-time (TAT) detractors in today's chip design. Coupling plays a major role in causing a large number of post-routing timing violations. Design “sign-off” requires that all such violations be corrected prior to releasing the design to manufacturing. To achieve an acceptable TAT, it is necessary to identify and repair such sign-off level effects early in the design process.
In the physical synthesis phase, design decisions are made at a given design stage based on predictions of the timing values that are to be determined after the design process is complete. For example, before placement, timing estimation must anticipate the effects of placement and routing that have not yet been performed, and to that end, various wire load models (e.g., estimated wire capacitance and resistance based on net fan-out) are used to approximate the timing. Similarly, when circuits have been placed but not routed, estimated Steiner routes can be used to predict the later timing impacts of actual wiring. While Steiner estimates are generally close to the final routing results, on occasion, the actual routes can be significantly longer than predicted, e.g., due to the need to route around blockages or congestion. A wire route for a net may be considered “long” if its total length (the sum of the lengths of all segments of the wire route) exceeds by more than some specified amount (e.g., 30%) an estimate of that net's total length made before routing. The process of predicting timing and electrical effects of subsequent design steps is not new to timing/design closure, but it is important that these estimates be as accurate as possible while not requiring excessive computation expense.
The increased effective capacitance of a net due to coupling or long wire routes not only affects the delay of that net and its driver, but also increases or degrades the slew (the time the signal takes to make a transition) at the gate output and net sink. Because gate delays and output slews are typically functions of input slew, any increase in the input slew of a gate due to coupling or long wire routes will also have a propagated effect on the delays of gates in the fan-out cone of the affected net.
Three approaches exist to predict timing effects of long wires or coupling early in the design process:                1. One can assume coupling/long wire routes for all the nets in the design, but this is highly pessimistic and can lead to considerable over-design and/or difficulty in closing timing.        2. One can include some built-in pessimism in the electrical parasitic extraction parameters used with estimated Steiner routes to take into account potential coupling capacitance or long wire routes that cannot be known until later in the design process. These default estimates for capacitance per micron of wire length have coupling capacitance and long routing effects taken into account. To avoid excessive pessimism, where inbuilt pessimism typically accounts for only a fraction of the potential impact of a true coupling event or long wire route on any net, and hence can be optimistic for short paths, with the cumulative impact of these pessimistic electrical parameters still less than the impact of a single true coupling event or long wire route. It also fails to account for the delay impacts of propagated slew degradation due to a coupling event or a long wire route.        3. The fault-tolerant static timing analysis approach described in U.S. Pat. No. 6,795,951 can capture the local impact of a predetermined number of coupling events and/or long wire routes along any path, but is expensive due to duplication of the timing graph. It takes into account propagated effects, but the cost is 2N+1 times the regular work, where N is the number of ‘faults’ or ‘events’ that may be considered along any timing path.        